Good day,
I want to refresh and (or) update my knowledge on ARMv7.
Is it true for ARMv7-M that when CPU starts execute one instruction, PC value has already been updated/is being updated in parallel with address of the next instruction? Or PC is updated after execution? Or when? Can you provide reference to architecture manuals for this info?
Why I am asking this? I have hard-fault handler which captures current (when hard-fault occurs) context. When debugging that captured information I have PC value which was captured. I want to be sure is that value (a) is an address on an instruction on which hard-fault occurred, (b) is an address of the next instruction, which was intended to be executed after the one which hard-faulted, (c) it depends and can be either (a) or (b) and where to look for info to decide which of (a) an (b) may be true for the specific situation. And there also may be (d) for this: is a value of PC when PC was being updated by instruction in execution progress..
Thank you in advance!
There are several type of behaviors - depending on use cases:
- if you read the PC value directly using MOV instruction, (from memory) you should see the result is instruction address + 4.
- if using PC as an offset for load instruction (i.e. LDR Rn, [PC, #offset]), you should also see the +4 offset, but in some cases the bit[1:0] of the address could be forced to 0 to make a word size lteral load word aligned. (http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/BABJJAAA.html)
- In the case of faults triggered by load and store instruction, then it depends on whether the bus access fault is synchronous or asynchronous (buffered write). For synchronous fault (load or non-bufferable store), the stacked PC is the same address as the faulting instruction. For bufferable write cases, then the stacked PC can be an instruction after the faulting instruction (because by the time the fault is received, the processor already started to execute subsequent instructions and the offset is unknown). You can tell if the fault is synchronous or not by reading the Configurable Fault Status Register (http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/Cihcfefj.html#Cihbeigb) (IMPRECISERR, PRECISERR, IBUSERR).
regards,
Joseph