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Is it possible to use the MPU to configure the Peripheral Memory Space as Execute?
It looks possible via the MPU_RBAR.XN bit.
If this is the case, is it fair to say that TrustZone aware select gates need to monitor HPROT[0] or PPROT[2] and block the transaction if it is an instruction fetch?
Regardless of MPU settings
the SG instruction must reside in a specific region type called
Non Secure Callable NSC
jumping to an SG instruction not in an NSC region results in a secure fault
only code in the secure side can configure a memory region as NSC using the SAU control registers
hence scenario is under control .