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Instruction Fetches from Peripheral Memory Space

Is it possible to use the MPU to configure the Peripheral Memory Space as Execute?

It looks possible via the MPU_RBAR.XN bit.

If this is the case, is it fair to say that TrustZone aware select gates need to monitor HPROT[0] or PPROT[2] and block the transaction if it is an instruction fetch?

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Ed Player over 7 years ago in reply to kappajacko +1 verified

You wrote: > I am not that knowledgeable on the MPU and want to confirm that the MPU can reconfigure > the Peripheral space from Execute Never to Execute. Yes, privileged code can reconfigure the MPU to...

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0 kappajacko over 7 years ago

Peripheral Memory Space being 0x40000000-0x5FFFFFFF.
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0 kappajacko over 7 years ago

Peripheral Memory Space being 0x40000000-0x5FFFFFFF.
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0 Diya Soubra over 7 years ago in reply to kappajacko

by the way, for those interested, ARM does offer training on developing SW for TrustZone for ARMv8-M

This course is designed for Software Engineers who already have development experience on ARMv6-M and/or ARMv7-M platforms and wish to gain experience of the TrustZone Security Extension introduced in ARMv8-M. This a public virtual training course that will help you to gain knowledge of the new feature...

https://developer.arm.com/support/training
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