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Speculative Branching.

sammy

Hi, I am new to ARM Cortex M3 Microprocessors. Can somebody please explain me the speculative branching in layman terms.

Thanks in advance.

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  • +1
    In Cortex-M3 and Cortex-M4, the pipeline is 3 stages, and the bus interface is also pipelined (consists of address phase, followed by data phase).

    Without speculative branch target fetch, the processor need to made the decision about branch in the 3rd pipeline stage (execution), and then output the branch target in the next clock cycle if the branch is taken, and then another clock cycle for the instruction to be available for reading into the processor.

    The branch penalty is a bit high in such arrangement, so we added speculative prefetching of branch target:
    When there is a conditional branch in the 2nd stage, the processor can output the branch target address in the bus (address phase) speculatively, so that when the branch decision is made by the end of the clock cycle, the memory system is ready to deliver the instruction in the next cycle. If the branch is not taken, that fetched instruction is discarded (it is okay as we have a 3 word instruction buffer inside the processor which hold a subsequent instruction).
    regards,
    Joseph
Reply
  • +1
    In Cortex-M3 and Cortex-M4, the pipeline is 3 stages, and the bus interface is also pipelined (consists of address phase, followed by data phase).

    Without speculative branch target fetch, the processor need to made the decision about branch in the 3rd pipeline stage (execution), and then output the branch target in the next clock cycle if the branch is taken, and then another clock cycle for the instruction to be available for reading into the processor.

    The branch penalty is a bit high in such arrangement, so we added speculative prefetching of branch target:
    When there is a conditional branch in the 2nd stage, the processor can output the branch target address in the bus (address phase) speculatively, so that when the branch decision is made by the end of the clock cycle, the memory system is ready to deliver the instruction in the next cycle. If the branch is not taken, that fetched instruction is discarded (it is okay as we have a 3 word instruction buffer inside the processor which hold a subsequent instruction).
    regards,
    Joseph
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