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Cortex-R7 ABT-Exception on Programstart

Martin K.

Hello,

I have a question about a strange behaviour which I have on a Cortex-R7 Core. I start a peace of firmware in an SRAM via a debugger. Before my Testcode starts, the core has the following state:

-> Core CPSR=0x000000d3: E=0 | A=0 | I=1 | F=1 | T=0 | MODE=SVC

After loading my firmware to the sram an start it and stop it again after some time the cpu has the following state

-> CPSR=0x000001d7: E=0 | A=1 | I=1 | F=1 | T=0 | MODE=ABT

The Testcode itself is an endless loop with some nop's in ARM32 Mode.

 

I also examining  the IFSR register and see the following values:

->IFSR=0x0000000D

In the ARM v7 reference manual the description of the register tells me that FS(3:0) == 0b01101 means MMU fault. But I have disabled the MMU through the SCTLR (mcr 15, 0, r0, cr1, cr0, {0}) write.

So I'm a bit puzzled why I get a MMU fault.

 

 

 

Parents
  • +1 Arm Employee Badge
    The Cortex-R7 has a MPU, not a MMU. Make sure that you read the description of IFSR in the PMSA chapter of the ARM ARM, and not the one in the VMSA chapter.

    For cores with a MPU, when it's disabled you get a default region set (chapter B5.1.5 of the ARMv7-A/R Architecture Reference Manual). As what you're seeing a permission I suspect you've loaded the code to an address which isn't executable in the default region set.

    What address is the code trying to run from?
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  • +1 Arm Employee Badge
    The Cortex-R7 has a MPU, not a MMU. Make sure that you read the description of IFSR in the PMSA chapter of the ARM ARM, and not the one in the VMSA chapter.

    For cores with a MPU, when it's disabled you get a default region set (chapter B5.1.5 of the ARMv7-A/R Architecture Reference Manual). As what you're seeing a permission I suspect you've loaded the code to an address which isn't executable in the default region set.

    What address is the code trying to run from?
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  • 0 in reply to Martin Weidmann

    Hello,

    thank you for your help

    unfortunately I cannot write the address in a public forum. But after table B5-1 "Default Memory" map my address located in an Execute-Never Area.

    I have tried to setup the MPU with a 4 GiB Area by writing the corresponding coprocessor register from the debugger. I set all available 16 regions to a 4GiB and finally enable the MPU in bit 0 of SCTLR  Area. Here are the contents after the setup:

    RGNR=00000000; DBAR=00000000; DRSR=0000003f, DRACR=00000301
    RGNR=00000001; DBAR=00000000; DRSR=0000003f, DRACR=00000301
    RGNR=00000002; DBAR=00000000; DRSR=0000003f, DRACR=00000301
    RGNR=00000003; DBAR=00000000; DRSR=0000003f, DRACR=00000301
    RGNR=00000004; DBAR=00000000; DRSR=0000003f, DRACR=00000301
    RGNR=00000005; DBAR=00000000; DRSR=0000003f, DRACR=00000301
    RGNR=00000006; DBAR=00000000; DRSR=0000003f, DRACR=00000301
    RGNR=00000007; DBAR=00000000; DRSR=0000003f, DRACR=00000301
    RGNR=00000008; DBAR=00000000; DRSR=0000003f, DRACR=00000301
    RGNR=00000009; DBAR=00000000; DRSR=0000003f, DRACR=00000301
    RGNR=0000000a; DBAR=00000000; DRSR=0000003f, DRACR=00000301
    RGNR=0000000b; DBAR=00000000; DRSR=0000003f, DRACR=00000301
    RGNR=0000000c; DBAR=00000000; DRSR=0000003f, DRACR=00000301
    RGNR=0000000d; DBAR=00000000; DRSR=0000003f, DRACR=00000301
    RGNR=0000000e; DBAR=00000000; DRSR=0000003f, DRACR=00000301
    RGNR=0000000f; DBAR=00000000; DRSR=0000003f, DRACR=00000301

    SCTLR=0x00C5007B

     

    But the problem remains the same. Maybe are there is something wrong with my setup?