In AXI, does the rising and falling edge of the WVALID signal signify the start and end of a write burst? Can the WVALID signal go low before the write request for all the transfers in that burst are issued?
No, WVALID does not have to be asserted continuously for a write burst. It's obviously better for bandwidth utilisation if a write transaction sees all of it's data transfers happen back to back, but the specification does not mandate it. For example, in a 4 beat burst, the master could transfer 2 beats, take WVALID low for a few cycles and then take it high again to complete the last 2 beats.
Hope that answers your question.
suppose master takes more clock cycles, if burst length is 256 then for how long the slave as to wait for the data.
The slave would have to wait for as long as the master needs. There isn't any protocol defined maximum number of cycles a transaction can take, or even a single transfer in a transaction. If the master doesn't yet have the data for a transfer available, the slave can't do anything but wait.
However if this was a common occurrence from this master, you would seriously need to look at the master design, and decide if it issuing multi-transfer transactions was appropriate, knowing that it could be stalling the system waiting for each long transfer to complete. It might be better for the system performance if that master instead just issued AxLEN=0 (1 transfer) transactions, or perhaps use buffers to store up transfers so that there is data available to then issue in a longer transaction.
But 256 transfers is a lot to buffer up, so it might be better for this master to use shorter transactions, and use buffers to make sure all the data is available to send in a series of consecutive transfers.