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why do we need two priviledged modes? cant one do the thing in cortex m3

sana srikar

we have two modes which are privileged in ARM cortex M3 .they are Thread privileged  and handler mode .

if there is already one privileged mode then why we need the other mode? i mean cant we do work with only one privileged mode?

is there any difference between Thread Privileged and handler mode?(i know that cortex m3 executes ISR in handler mode what are the other differences)

are there things which thread privileged mode cannot access and handler mode can access?

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  • +2 in reply to sana srikar

    Hi srikar ,

    Well, let we think about it from another aspect.
    Cortex-M3 and M4 would be used in the higher embedded areas, and they would use sometimes RTOS. If an OS is used, there are two execution modes such as the user and the system (or supervisor) would be defined for resource protection.
    I quess ARM assume the following configurations for Cortex-M3 and M4 execution modes.
    - User = Thread = Unpriviledged = SP_process
    - System = Handler = Priviledged = SP_main
    However, ARMv7-M architecture permits the other combinations for the flexibility.
    For exsample, Cortex-M0 has no Unpriviledged Thread mode and Cortex-M0+'s Unpriviledged Thread mode is an option, although they equip ARMv6-M Architecture. They are for lower end embedded areas, and usually any OS would not be used. Therefore, basically thay have only Priviledged modes.

    Best regards,

    Yasuhiko Koumoto.

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  • +2 in reply to sana srikar

    Hi srikar ,

    Well, let we think about it from another aspect.
    Cortex-M3 and M4 would be used in the higher embedded areas, and they would use sometimes RTOS. If an OS is used, there are two execution modes such as the user and the system (or supervisor) would be defined for resource protection.
    I quess ARM assume the following configurations for Cortex-M3 and M4 execution modes.
    - User = Thread = Unpriviledged = SP_process
    - System = Handler = Priviledged = SP_main
    However, ARMv7-M architecture permits the other combinations for the flexibility.
    For exsample, Cortex-M0 has no Unpriviledged Thread mode and Cortex-M0+'s Unpriviledged Thread mode is an option, although they equip ARMv6-M Architecture. They are for lower end embedded areas, and usually any OS would not be used. Therefore, basically thay have only Priviledged modes.

    Best regards,

    Yasuhiko Koumoto.

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