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In AXI Interface, is the VALID signal of the master dependent on the slave's READY signal

Ramesh Babu R

Hi,

I am seeing an issue, where the READY signal's assertion depends on the VALID signal. If the VALID signal remains asserted through out the transaction (Say, for a burst transfer), then for the second burst beat to occur, the WREADY should have been asserted by slave, but didn't assert, as the VALID is high.

Can you confirm, whether VALID signal should be dependent on the READY signal.

Thanks.

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  • +1

    Hi rbabu,

    Can you confirm, whether VALID signal should be dependent on the READY signal.

    VALID signal MUST NOT be dependent on the READY signal.
    Please refer to the AXI Specs (IHI0022E). The followings are described.

    A3.3.1 Dependencies between channel handshake signals
    To prevent a deadlock situation, the dependency rules that exist between the handshake signals must be observed.
    As summarized in Channel signaling requirements on page A3-40, in any transaction:
    • the VALID signal of the AXI interface sending information must not be dependent on the READY signal of the AXI interface receiving that information
    • an AXI interface that is receiving information can wait until it detects a VALID signal before it asserts its corresponding READY signal.
    Note
    While it is acceptable to wait for VALID to be asserted before asserting READY, it is also acceptable to assert READY before detecting the corresponding VALID. This can result in a more efficient design

    To the contrary, the READY signal can be dependent on the VALID signal.
    Therefore, your system might be right.
    The cause of no assertion of WREADY might be why the slave could not accept the 2nd beat address.

    Best regards.
    Yasuhiko Koumoto.

Reply
  • +1

    Hi rbabu,

    Can you confirm, whether VALID signal should be dependent on the READY signal.

    VALID signal MUST NOT be dependent on the READY signal.
    Please refer to the AXI Specs (IHI0022E). The followings are described.

    A3.3.1 Dependencies between channel handshake signals
    To prevent a deadlock situation, the dependency rules that exist between the handshake signals must be observed.
    As summarized in Channel signaling requirements on page A3-40, in any transaction:
    • the VALID signal of the AXI interface sending information must not be dependent on the READY signal of the AXI interface receiving that information
    • an AXI interface that is receiving information can wait until it detects a VALID signal before it asserts its corresponding READY signal.
    Note
    While it is acceptable to wait for VALID to be asserted before asserting READY, it is also acceptable to assert READY before detecting the corresponding VALID. This can result in a more efficient design

    To the contrary, the READY signal can be dependent on the VALID signal.
    Therefore, your system might be right.
    The cause of no assertion of WREADY might be why the slave could not accept the 2nd beat address.

    Best regards.
    Yasuhiko Koumoto.

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