Hi,
I have a A53 with 2 clusters with 4 cores each. Not planning to use EL2. I have a question on how the translation tables need to be setup for Arch64. with 4KB granule, 4GB PA
for EL3 I have level1, level2, level3 tables.
1) can the translation tables be shared between EL3 and EL0, EL1 ?
2) If need to use both TTBR0_EL1 and TTBR1_EL1, does this need separate set of tables?
Does ARM provide any guidelines on how the tables are shared?
thanks
PS
Hiya,
Generally you wouldn't want to have the exact same view of memory for EL3 (which is usually where your firmware lives) and EL1/0 which is your OS and user-space. You can see this in practice in the ARM Trusted Firmware, it maintains its own tables at EL3 and then lets Linux manage the EL1/0 tables. EL3 is a secure state so the first step of any table walk will be a secure access which makes sharing these tables problematic from a practical standpoint.
If you are building your won simple SW stack and don't intend to really use EL3 past boot time you could potentially not enable the EL3 MMU and just use a flat mapping.
At EL1/0 TTBR0_EL1 maps teh bottom virtual addresses (0 and up) and TTBR1_EL1 maps the high virtual address space. If you don't use the top virtual addresses you don't need to use TTBR1 at all.
Pete.