Hi,
As I have found in:
Cortex-M0+ Devices Generic User Guide: 2.1.3. Core registers
There is information about instruction behaviour during interrupts:
The interruptible-restartable instructions are LDM, STM, PUSH, POP and, in 32-cycle multiplier implementations, MULS. When an interrupt occurs during the execution of one of these instructions, the processor abandons execution of the instruction. After servicing the interrupt, the processor restarts execution of the instruction from the beginning."
LDM
STM
PUSH
POP
MULS
This is good information, now I would also like to know how instructions like str and ldr behave during interrupt, and whether unaligned loads will behave differently for instance.
To give example on what I was hoping for one can have a look at "EREF: A Programmer’s Reference Manual
for Freescale Power Architecture Processors".
"8.9 Partially Executed Instructions
In general, the architecture permits load and store instructions to be partially executed, interrupted, and
then restarted from the beginning upon return from the interrupt. To guarantee that a particular load or store
instruction completes without being interrupted and restarted, software must mark the memory as guarded
and use an elementary (non-multiple) load or store aligned on an operand-sized boundary.
To guarantee that load and store instructions can, in general, be restarted and completed correctly without
software intervention, the following rules apply when an interrupt occurs after partial execution:
• For an elementary load, no part of a target register (for example, rD or frD) has been altered.
• For update forms of load or store, the update register, rA, will not have been altered (note these are
invalid forms).
The following effects are permissible when certain instructions are partially executed and then restarted:..."
After that follows vastly more information about special cases. I hope ARM is simpler than PowerPC and that the statement at the top is just whats needed and other instructions are just not interrupted but would like to find some confirmation of this ideally in ARMs literature.
If you would help me find it I would be glad.
Regards,
Kilian
Although I cannot still catch the intention of your question, the means of 'can' is to process (or continue) without inconsistency.
It will not include such interruptible instructions as LDM and STM. because there will be some bad scenarios which the restart will cause inconsistency if the operands specified the device which could not be access more than twice such as FIFOs.
The normal instructions other than so called interruptible-restartable instructions are not interrupted by an interrupt while executing and are interrupted after execution.
Therefore the stacked PC on the interrupt stack is the next PC for normal instructions.
Regarding the interruptible-restartable instructions, the current PC is put on the interrupt stack.
Can the above become answer of your question?
Best regards,
Yasuhiko Koumoto.
Thanks that helps. I'm working on something functional safety related, so I better make sure. I'm also paranoid about squishy words like 'can'.
Best Regards,