Since I am currently reading lot of ARM documents to understand the architecture as a whole, I request you to mention as to what happens in case of CORTEX-A processor in the nested interrupt handler implementation since we have a SPSR in CORTEX-A processors. My understanding is interrupt is disabled for brief period to save the CPSR_IRQ to SPSR_SYS and also save the system mode registers before handling the new interrupt. Correct me If I am wrong.