Since I am currently reading lot of ARM documents to understand the architecture as a whole, I request you to mention as to what happens in case of CORTEX-A processor in the nested interrupt handler implementation since we have a SPSR in CORTEX-A processors. My understanding is interrupt is disabled for brief period to save the CPSR_IRQ to SPSR_SYS and also save the system mode registers before handling the new interrupt. Correct me If I am wrong.
msd it really depends on the Execution State of the exception level. For ARMv7 and ARMv8 AArch32, on entry to an IRQ exception [handler], the core will mask IRQ exceptions in the CPSR. The SPSR will reflect the previous state before the exception was taken and, in general, IRQs are not masked in the SPSR (otherwise you would never have taken the IRQ exception in the first place. Hypervisors and Secure Monitors notwithstanding).
A nested implementation would save the current SPSR_irq and LR_irq (there are many ways to do this, even a set of instructions -- SRS and RFE) and then modify the CPSR (using MSR or CPSIE) to unmask the appropriate exception. Before returning from the exception, it would modify the CPSR (again using MSR or CPSID) and then, and only then, restore SPSR_irq and LR_irq from their first states.
For entry to FIQ, IRQ and FIQ are masked in the CPSR on entry to the exception.
For ARMv8 AArch64, the model is slightly different -- upon entry to ANY exception, all masks are set in PSTATE. The process is roughly the same -- save off SPSR_ELx and ELR_ELx, then unmask the appropriate exceptions, then before exception return (ERET), enable the masks again and restore the SPSR_ELx and ELR_ELx values,