Hello,
What is the purpose of the RSDIS (Return Stack DISable) bit in ACTLR ?
What would be the consequence on code execution if set DISable ?
Is the software able to write this bit ?
Thanks for help
Hi Sylvain,
RSDIS enables (RSDIS=0) or disables (RSDIS=1) the return address stack used in procedure call/return program flow prediction.
In Cortex-R4/R5, if program flow prediction is not entirely disabled (by also setting the branch prediction policy to always not-taken), the remaining branch prediction schemes are still in effect.
For programs that can exploit the procedure call/return program flow prediction, the enhancement in execution speed if the return address stack is ENABLED can be estimated through some data provided in Cortex-R4/R5 TRMs. Here are some excerpts from Cortex-R5 TRM Rev. r1p2 (ARM DDI 0460D) section B.9 Branches:
From page B-15, Table B-10 shows that for the two BX instruction formats, execution is 9x faster if return stack prediction is CORRECT.
From page B-17, Table B-13 shows LDR to PC instructions, execution can be up to 9x faster if return stack prediction is CORRECT.
From page B-21, Table B-18 shows LDMIAs with PC in register list, there are additional 8 cycles if return stack prediction is INCORRECT.
In most cases, I think a disabled return address stack is equivalent to incorrect return stack prediction in terms of the number of cycles needed in executing the type of instructions cited in the tables.
Generally, ACTLR (where RSDIS is contained) is a Read/Write register but accessible in privileged mode only.
For Cortex-A5, there are also additional caveats:
In Non-secure state,
Attempts to write to ACTLR in secure privileged modes when CP15SDISABLE is HIGH result in an Undefined instruction exception.
Regards,
Goodwin
For Table B-13 I stated execution can be up to 9x faster but I failed to include the Memory cycle. It should be either up to 5x faster if return stack prediction is CORRECT or there are additional 8 cycles if return stack prediction is INCORRECT.