Hello,
What is the purpose of the RSDIS (Return Stack DISable) bit in ACTLR ?
What would be the consequence on code execution if set DISable ?
Is the software able to write this bit ?
Thanks for help
Hello syl,
as the result, the RSDIS=1 disables the return address prediction from a function.
Please refer to the following descriptions from "Cortex™-R4 and Cortex-R4F Technical Reference Manual Revision: r1p4 (ARM DDI 0363G)".
5.3. Return stack
The call-return stack predicts procedural returns that are program flow changes such as loads, and branch register. The dynamic branch predictor determines if conditional procedure returns are predicted as taken or not-taken. The return stack predicts the target address for unconditional procedure returns, and conditional procedure returns that have been predicted as taken by the branch predictor.
The return stack consists of a 4-entry circular buffer. When the PFU detects a taken procedure call instruction, the PFU pushes the return address onto the return stack. The instructions that the PFU recognizes as procedure calls are:
•for ARM and Thumb instructions:
â—¦BL immediate
â—¦BLX immediate
â—¦BLX Rm.
When the return stack detects a taken return instruction, the PFU issues an instruction fetch from the location at the top of the return stack, and pops the return stack. The instructions that the PFU recognizes as procedure returns are, in both the ARM and Thumb instruction sets:
•POP {..,pc}
•LDMIB Rn{!}, {..,pc}
•LDMDA Rn{!}, {..,pc}
•LDMDB Rn{!}, {..,pc}
•LDR pc, [sp], #4
•BX Rm.
Return stack mispredictions can exist when:
•The prediction that a conditional return passed or failed its condition code is not correct.
•The return address is not correct. The DPU resolves indirect branches that the return stack predicts at the Ret-stage of the pipeline, see Figure 1.3. A misprediction causes the PFU to flush the pipeline and fetch the correct instruction stream.
The return stack has no underflow or overflow detection. Either scenario is likely to cause a misprediction.
Note
The MOV PC, LR instruction is not decoded and is not predicted as a return.
5.4. Controlling instruction prefetch and program flow predictionYou can disable the return stack by setting RSDIS in the ACTLR. When disabled, pushes onto the stack caused by call instructions are disabled, but the stack pointer is not frozen.
Best regards,
Yasuhiko Koumoto.
Thanks Yasuhiko,
The answer is very clear.
Note there is a discrepancy with the text in Cortex R5 TRM DDI0460D about stack pointer :
"...When disabled, pushes onto the stack caused by call instructions are disabled and the stack pointer is frozen."
Which document is right ?
Sylvain
Hi,
I checked the Cortex R5 TRM DDI0460D and found the same description in chapter 5.4 as "and the stack pointer is frozen".
I cannot find any discrepancies.
The stack pointer in the sentence "and the stack pointer is frozen" will be one of the return stack which holds the predicted return addresses.
I am afraid you are thinking of the normal stack pointer which is denoted as R13.
R13 and the return stack pointer are not equal registers.
I was comparing the DDI460D text to your first answer which quotes "...is not frozen" ( extract of ARM DDI 0363G).
They are different : first one says frozen, second one sys not frozen
I don't think this makes any difference in processor behavior but it remains the documents are not coherent.
Oh!,
I'm sorry but I had been overlooked.
I think that the return stack is not frozen for Cortex-R4 and is frozen for Cortex-R5.
Anyway, it would not a big issue because the return stack pointer is invisible.
There are discrepancies between the two documents but in this case it is not an error. When RSDIS is set, the return address stack pointer behaves differently in Cortex-R4 and Cortex-R5. If you will notice, when the prediction is forced to a fixed direction (through the BP field in the ACTLR), the global history table also behaves differently.