Hello,
I am preparing for the AAE. ARM is a modified Harvard architecture. What is this about ? I searched in internet and got various answers.
Can anyone tell me exactly what is this modified Harvard architecture in ARM's point of view ? Please point to any relevant literature.
Regards,
Deepu
goodwin wrote:As you can see from the list, Harvard architecture features are implemented only at the pipeline and cache and this modification is generally transparent to the programmer.
goodwin wrote:
As you can see from the list, Harvard architecture features are implemented only at the pipeline and cache and this modification is generally transparent to the programmer.
As an addition to that, while it is still technically transparent to the programmer, it is possible that the type of access actually makes it onto the unified bus -- AHB HPROT[0] and AXI AxPROT[2] signals will usually tell you, if it is at all differentiated once it gets past the core, whether it originated as an instruction or data access. Obviously this makes far more sense on the read path (towards the core) where either the data or instruction side may be reading what it intends to be instructions or data -- however a unified cache at any level may obfuscate this. A write transaction over the bus would never be marked as an instruction access even if the data contains instruction opcodes, because explicit loads and stores are data accesses, and an instruction cache has no business writing to memory.
Where it may not be transparent to the programmer is if particular peripherals within the SoC design actually respected PROT[2] and denied or somehow differently arbitrated an instruction access. For instance, it makes no sense at all for instructions to be fetched from a DMA controller peripheral register set, but it does from a (RAM or ROM) memory region. One may mark particular areas of Flash peripherals as instruction or data only access, depending on the peripheral design. In that sense, you would see actual feedback as to whether the access was valid or not, and therefore some semblance of a Harvard architecture.
The real distinction is that a modified Harvard architecture still has separated instruction and data paths, but doesn't split the memory space. In a true Harvard architecture, a data access could never happen to the instruction address space, and an instruction fetch could never happen to the data address space -- in theory they'd be completely demarcated. This is really inconvenient for self-modifying code, however and makes loading applications on-demand really complicated, so pretty much all modern computing steers well clear of it.
For the Cortex-R and Cortex-M where there are TCMs, the address space for the instruction and data TCM is exactly the same -- although some cores allow overlapping TCM regions, it is usual for data accesses to be prioritized above instruction accesses meaning you see a different view from an instruction fetch perspective than you would from a load/store or a bus-generated access for the same address.