Hello,
I am preparing for the AAE. ARM is a modified Harvard architecture. What is this about ? I searched in internet and got various answers.
Can anyone tell me exactly what is this modified Harvard architecture in ARM's point of view ? Please point to any relevant literature.
Regards,
Deepu
I find the above answers great and very informative. I have a small detail to add:
On true von Neumann architectures, you will also find that the number of clock cycles for each instruction is fixed.
For instance, you will know that on a Cortex-M0, a LDR instruction always takes 2 clock cycles.
However, on Cortex-M3, Cortex-M4 and Cortex-M7, pipelining is available.
That means the instruction timing is variable on these cores.
The LDR instruction on the Cortex-M3, for instance, may be pipelined with another LDR instruction and result in using a total of 3 clock cycles for two LDR instructions instead of 4.
This means that you can optimize your code by simply placing the LDR instructions in one block and the data processing instructions in another block.
It also means that if you're writing code that needs to run in a tight timing, you will have to be careful if the code needs to be executed on both Cortex-M0 and Cortex-M4 for instance.