Hi,
Assume system configuration is: CM4 in a switchable power domain and WIC in always on domain. Also in response to "seeldeep" if the power management unit is powering down the CM4 and with no logic retention.
Given this system configuration, power management unit powers the CortexM4 in response to "sleepdeep". When power management unit receives a wake up event from WIC, it powers up the CM4 and de-asserts por and sys resets. When CM4 is powered up and out of reset, does it generate WICCLEAR signal to clear the WIC?
Regards,
Dhaval
In that case you could design your Power Management Unit (PMU) to add an extra signal to clear/reset WIC when the processor system is up and running. Usually the PMU contains a FSM, and adding such output is easy. For example, you can generate a WICCLEAR from the PMU's FSM, and the WICCLEAR is OR together with the WICCLEAR from the Cortex-M processor. So either the WICCLEAR from the processor or the WICCLEAR from the PMU can clear the WIC.
Joseph,
Thanks you very much for the prompt reply. Really appreciate it.
I understand your suggestion about the PMU incorporating WICCLEAR signal, that is certainly a good idea.
Just to be concrete, you confirm that CM4 does not assert WICCLEAR signal in the scenario mentioned above (where we power down and reboot the core by asserting-deasserting por and sys resets). I have a simulation that shows no WICCLEAR assertion and I want to make sure we are not making any mistakes in integration that is causing this (no assertion of WICCLEAR) to happen.
Thanks once again.
That's right. When the Cortex-M4 come out from reset it won't assert WICCLEAR.
regards,
Joseph