Is the isb necessary between modifying ttbr and flushing TLB?

I encountered a problem about replacing the active TTBR0_EL2 register. It seems that the new data loading does not use the new page table, or the instruction execution is messed up. In short, Data Abort is triggered, and ISS indicates that the error details are at translation level 1.

I compared the process of modifying the page table base address in the Linux kernel and found that the Linux kernel added an `isb` instruction between modifying ttbr and TLB refresh. So I added it and found that everything worked fine. I read the ARM manual and some online information, but I didn't figure out why.

1. why memory barrier is needed?
2. if yes, why can't use `dsb` replaced?

Configuration: MMU on, dcache off, icache off

```asm
; linux/arch/arm64/mm/proc.S
.macro        __idmap_cpu_set_reserved_ttbr1, tmp1, tmp2
        adrp        \tmp1, reserved_pg_dir
        phys_to_ttbr \tmp2, \tmp1
        offset_ttbr1 \tmp2, \tmp1
        msr        ttbr1_el1, \tmp2
        isb 
        tlbi        vmalle1
        dsb        nsh
        isb
.endm
```