Hi all,
I refer to the section "Direct access to internal memory" in Arm A55.
I believe the way to extract L1 Data cache data is by first write/MRS index/set/way into register CDBGDCD_EL3, then read back 64B via the CDBGDR0..3_EL3.
The L1D cache line is 64B, but 4 Xd can only read out 32B. What is the catch here?
How is the index/set/way encoded in the Xd to select a particular line?
Thank you for your input.
User_0182