Dear Expert
We would like to disable the speculative memory accesses of L1.Is the way to disable above function?
We found "I bit of SCTRL" controls the function of Instruction Caches.If we negate that bit, are both Instruction Caches and the speculative memory accesses disabled?
If we would like to disable the speculative memory accesses alone, how should we do?
We use the processor of A15 (revision r2p2).
Regards.
The Arm Architecture Reference Manual for Armv7 is probably a better reference than the TRM in this case.
https://developer.arm.com/documentation/ddi0406/cd/?lang=en
The descriptor format is described on page B3-1324, Figure B3-5 Short-descriptor second-level descriptor formats.
The usual recommendation is that all Device and SO regions are XN=1, plus any Normal regions that instructions shouldn't be fetched from.
Thanks for your reply.
I understand how we achieve the 4k mapping.
Reading the contents in the Reference Manual, we think the Long-Descriptor table with 3rd level(B3.6) can also enable us to set XN ranges in units of 4k bytes.Is that correct?
As we implement the processor code with Texas Instruments API for using the TI processor, we prefer to implement with Long-Descriptor table.TI API assumes the Long-Descriptor table.
<Link>https://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/bios/sysbios/6_70_00_21/exports/bios_6_70_00_21/docs/cdoc/ti/sysbios/family/arm/a15/Mmu.html