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[Cortex-A15/Arm7v]Is the way to disable the speculative memory accesses of L1

Dear Expert

We would like to disable the speculative memory accesses of L1.
Is the way to disable above function?

We found "I bit of SCTRL" controls the function of Instruction Caches.
If we negate that bit,  are both Instruction Caches and the speculative memory accesses disabled?

If we would like to disable the speculative memory accesses alone, how should we do?

We use the processor of A15 (revision  r2p2).

Regards.

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