I am working on intel cyclone 5 hps I have two cores in a processor Core 0 core 1, I want two code to run on two different cores core 0 and core 1 in bare metal .
When I run in jtag mode it works, for jtag i first debug using core 0 where i take core 1 out of reset it, than debug core 1 usign jtag it work
BUT, When i want to run both core usign qspi it only run core 0 not core 1
Here is the step i followed
Firsly, loading preloaderquartus_hps -c 1 -o P preloader-mkpimage.bin
I make an image from bin file of core 0 and place it to qspi
mkimage -A arm -O u-boot -T standalone -C none -a 0x00060000 -e 0 -n "baremetal image" -d core0.bin core0.img
quartus_hps -c 1 -o P -a 0x00060000 core0.img
I make an image from bin file of core 1 and place it to qspimkimage -A arm -O u-boot -T standalone -C none -a 0x00100000 -e 0 -n "baremetal image" -d core1.bin core1.imgquartus_hps -c 1 -o P -a 0x00100000 core1.bin
When i restart board only that code work which is in core 0, core 1 code not executing
I am setting cpu1startaddress 100000 apart from that in the code of core 0 also i am using alt_qspi function to to place bin file data in ddr,
I want to run in smp mode so I also set required aux_control_register smp and fw bit as stated in tech ref manual
alt_qspi_read((uint32_t *)BL_START/*ddr3 address*/, 0x100000/*qspi address*/, 0x40000);
In linker/scat file core 0 entry point is 0x60000 and
linker/scat file core 1 entry point is 0x100000
I have asked in many forums but no reasonable response, I asked here as issue is related to ARM Cortex A9 Dual core bringup
I am working on an Intel Cyclone V SoC ARM Cortex A9 Dual Core setup and aiming to execute two distinct codes on Core 0 and Core 1 in bare-metal mode. While I've successfully executed this setup using JTAG debugging, where I sequentially debugged Core 0 followed by Core 1 after taking it out of reset, I'm encountering a problem when attempting to run both cores via QSPI flash.
Despite combining both programs into a single image file, Core 1 fails to execute as expected. In the linker/scat file, Core 0's entry point is specified as 0x60000, and Core 1's entry point is set to 0x9fff0. **However, upon execution, Core 0 behaves correctly, while Core 1's program counter jumps to 0xFEBAF5E8 instead of its designated entry point.**
I have also asked in the intel community forum but no reasonable response. Your insights or suggestions on resolving this discrepancy would be greatly appreciated.
Thank you!