Hi, I make a software for Cortex-A9 and Cortex-M4 (both uni-processor system).
Question.
Is 64bit-aligned STRD(64bit memory access) atomic ?
(I know tha It is not atomic, but i don't know behavior.)
For example:
LDR R2,=buff
mov R0, #1
mov R1, #2
STRD R0, R1, [R2]
mov R0, #3
mov R1, #4
STRD R0, R1, [R2] <- interrupt occerd
handler:
LDR R0, R1, [R2] <--- ???
Is[R0,R1] == [#3, #2] may?
If it is, require disable-interrupt between STRD?
Some background, ARMv7-A (which the Cortex-A9 implements) does not guarantee that LDRD/STRD are atomic.
However, the Large Physical Address Extension does (as long as the the address is 64-bit aligned). The Cortex-A7/Cortex-A15/Cortex-A17 all implement LPAE. This change was needed inpart because LPAE introduces 64-bit wide descriptors in the translation tables, and you need to be able update these atomically.
See section A3.5.3 of the ARMv7-A/R Architecture Reference Manual.