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What is the purpose of two separate coprocessors (CP10 and CP11) for the armv7-m floating point extension?

I've searched through the armv7-m manual and SoC datasheets regarding CP10 and CP11 for enabling floating point, and all of them say essentially the same thing:

The system must enable access to CP10 and CP11 in the CPACR before software can access the FP
extension system register,

and

If the access control bits are programmed differently for CP10 and CP11, operation of floating-point
features is UNPREDICTABLE.

If both coprocessors must be identically programmed, what is the point of having two separate ones? I haven't found any information or cases in which the two would be programmed differently, so why not just have one?

  • I believe the reason is to keep software compatibility from when VFP was a true co-processor.

  • Armv7-M defines a Coprocessor Access Control Register (CPACR) at address 0xE000ED88. Bits [23:20] of CPACR shall adopt the same behavior as defined in Armv7-A/R. This is consistent with application code being forward compatible between Armv7-M and Armv7-A/R, whilst allowing simplification in Armv7-M both in definition and implementation