Hi, ARM communities,
I have one question about how the peripherals are accessible when NW and SW (TrustZone) both need to access the same peripherals at the same time.
I know that the NS bit in the bus transaction is used to tell which transactions belong to which world, but I would like to understand how the device is shared between two different worlds.
Are the peripherals accessed exclusively by one of the two different worlds? or can peripheral support concurrent accesses from two different worlds securely?
For example, if NW and SW both want to load their GPU kernel into GPU, how does it work?
Do I need a software lock for allowing concurrent access? or does the monitor code provide exclusive access to GPU?
Also, I was wondering if this model can be different based on the form factors (e.g., mobile or server) and capabilities of peripherals.
Sincerely
Jaehyuk
The answer is that it depends, there are different models used by different devices. It really depends on the device, the use-case and what security guarantees you need to maintain. Which I appreciate is kind of a hand-wavy answer.
Very roughly: Is the device is TrustZone aware or not? Things like the GIC and SMMU can be natively aware of multiple Security states and can use the accessed PAS (i.e. the NS bit on the bus) to control what config/state/functionality is visible. Other devices, say a simple timer, might not be aware of multiple security states, relying on the memory-system to handle things like PAS enforcement.
Assuming a non-TrustZone aware device: For both Security states to be able to access a device then it must be a Non-secure device (as Non-secure state can't reach Secure PAs). So the next question would be - why is code in Secure world directly accessing a Non-secure device?
Perhaps a more likely model is one world owns the device, and provides a service to the other world. Such as Non-secure world owns the network, but there's a software interface for the Secure world to cause something to be sent or to receive data from the network.