Cortex M7 pipeline

Hello,

Currently, I am evaluating cortex M7 core for real-time audio signal processing in single precision floating point (FPU) using NXP1176 evaluation board.

I have few questions to fully exploit M7 core.

1. Can you point out the document that explains clearly the working of M7 pipeline and how to optimize the pipeline for floating point operations.
2. Can you provide me a table containing timing information (cycle count) for FPU instructions set?
3. M7 is a dual-issue core. Can you provide information (table) which instructions (FPU) can be executed parallel?
4. M7 support single cycle MAC operation (VFMA) but not in all situations. Can you identify scenarios where VFMA (or VLMA) can be executed

in single cycle?

1. Can we execute load (VLDR) and MAC operation (VFMA) in parallel in single cycle? If not, load 2 words (LDM) in integer unit + VFMA can be

executed in parallel. What is the plenty to transfer data from integer register to Floating point register and vice vera?

Thanks for your support.

Best Regards, 

Mussab Zubair