Hello all,
In a simple software test, the M55 is instructed to do successive writes at incrementing memory-mapped addresses in the SoC. When we open the waveform after the simulation, we observe that several writes are being skipped, or in some instances, the writes are being delayed and happened much later in the waveform. Some writes do occur successfully, but many fail. Therefore, what we are seeing in the post-simulation waveform does not match the sequence of instructions specified in our software C code. For example, in the embedded code shown below, I see in the waveform only the write at address 0x60.
We believe this is likely a software/driver issue rather than a hardware issue because our SoC also integrates a Cortex-M0 which has no problem writing 32-bit data at these same memory-mapped addresses. Our SoC integrates the M0, M55, and a custom-designed processor - which all interconnected via a configured NIC-400.
Please, any help, direction, or insight on dealing with this issue would be greatly appreciated. Thank you!
#define HW64_REG(ADDRESS) (*((volatile unsigned long long *)(ADDRESS))) #define ACCEL_BASE (0x33000000UL) //MEM0 data_64b = 0x00F4ED90F1C87960; HW64_REG(ACCEL_BASE) = data_64b; data_64b = 0x005B6762F7F3B940; HW64_REG(ACCEL_BASE +0x10) = data_64b; //MEM1 data_64b = 0x00F4ED90F1C87961; HW64_REG(ACCEL_BASE + 0x30) = data_64b; data_64b = 0x005B6762F7F3B941; HW64_REG(ACCEL_BASE +0x40) = data_64b; //MEM2 data_64b = 0x00F4ED90F1C87962; HW64_REG(ACCEL_BASE +0x60) = data_64b; data_64b = 0x005B6762F7F3B942; HW64_REG(ACCEL_BASE +0x70) = data_64b;