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ARM_M7(CYT4BFX) is slower than ARM_M4 (CYT2B9X)

Hello,

We are experiencing a high CPU load (95%)in the  System which is based on the “CYT4BFBCJE” (ARM_M7)microcontroller running at 160Mhz whereas the other system which is based on CYT2B9X(ARM_M4) has very less CPU load of 25% even though running at half clock speed of 80Mhz .

We are using same vector BSW ,BSW configuration and application software ,but M7 system is running slower than M4.We are using same compiler options in both systems. Not sure why ARM_M7 system is slower than ARM_M4 system.

Could you please help us possible ways to reduce CPU load in M7 system?.

What are steps to enable instruction cache?.

I just added a line SCB_EnableICache();  that reduced CPU Load by 57%.I did not chosen what part of flash memory can be catchable nor enabled MPU, could you please confirm is it okay to enable just instruction cache  alone with out enabling MPU?.

What are the steps to configure Data Cache?.

I followed following steps ,but after enabling MPU ,its going to exception for some reason. Could you please  confirm am I missing some thing here?.

1.ARM_MPU_SetRegionEx(0UL, 0x28050000,ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_16KB));

2.ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);

3.SCB_EnableDCache();

Regards,

Bhaskar

  • >What are steps to enable instruction cache?.

    On an Atmel ATSAMV71Q21B Cortex M7, I did this:

        SCB_InvalidateICache();
        SCB_EnableICache();
        SCB_InvalidateDCache();
        SCB_EnableDCache();

    You need to read carefully how the DMA system interacts with the cache.

    I am not experienced with the MPU.

    Best regards,