Hi,
Below is the connection.
My IP based on AXI-4 lite <-> 64bit -> Interconnect <-AXI4-> 64bit ARM A53
Upper 32bit data (ex addr: 0x1004) got cleared once I write lower 32bit data (ex addr: 0x1000) from ARM core to my IP registers and vice versa.
64bit (ex addr: 0x1000-0x1007) write and read seems to be working. So just looking into signals and need some insights.
Now my question is that when I perform narrower transactions on AXI4 from ARM to my IP through aforementioned connection how should be AWADDR & WSTRB signals for address 0x1004 upper 32bit txn ?
i) AWADDR = 0x1004 & WSTRB = 0xF0 ??
ii) AWADDR = 0x1000 & WSTRB = 0xF0 ??
I should set AWADDR as 0x1000 or 0x1004 in this case as per spec & standards ? because my IP expects 64bit boundary address, may be thats why lower 32bit data cleared when I write upper 32bit !?
PS: 0x1000 is 64bit boundary IP reg based on AXI-4 lite