ARM Cortex A-8 Bare-metal application with uboot

Hi,

In Beaglebone Black I'm trying to run a baremetal program (UART0 running in polling mode).

Using boot compiled using baremetal toolchain gcc-arm-none-eabi-10.3-2021.10 as Secound stage bootloader to load and run the baremetal program.

Uboot is compiled with config “am335x_evm_defconfig”. Copied MLO, u-boot.img from the uboot compiled to the SD-Card.

Compile the Baremetal program without vector table to run over uboot. In bare-metal program I have disabled FIQ and IRQ.

I'm try to run the application from two address both are behaving differently

Trying to load application to the RAM address 0x402f0400 from uboot - getting error "trying to overwrite reserved memory…"

$ fatload mmc 0 0x402f0400 helloworld

loading and running application from address 0x80000000 from uboot- baremetal program is running, but soon the target is restarting.

$ fatload mmc 0 0x80000000 helloworld

$ go 0x80000000

Below is the start-up code of the bare-metal application:

.globl _start

_start:
mrs r0, cpsr
bic r0, r0, #0x1F ;@ clear mode bits
orr r0, r0, #0x13 ;@ set SVC mode
orr r0, r0, #0xC0 ;@ disable FIQ and IRQ
msr cpsr, r0

mrc p15,0,r0,c1,c0,2 ;@ read cp access register
orr r0,r0,#0x00F00000 ;@ enable full access to neon/vfp (coproc 10&11)
mcr p15,0,r0,c1,c0,2 ;@ write cp access register
isb ;@ instruction synchronization barrier
mov r0,#0x40000000 ;@ switch on vfp & neon
vmsr fpexc,r0 ;@ set EN bit in fpexc

ldr sp, =0x4030CDFC ;@6kB public stack TRM 26.1.3.2, used when copying and running the program from  the RAM address 0x402f0400,
//ldr sp, =0x8030CDFC ;used when copying and running the program from  the RAM address 0x80000000
bl psr_main

.loop: b .loop

Below is the linker script of the baremetal program:

MEMORY
{
//RAM : ORIGIN = 0x80000000, LENGTH = 0x1B400 // used when copying and running the program from  the RAM address 0x80000000
RAM : ORIGIN = 0x402f0400, LENGTH = 0x1B400 // used when copying and running the program from  the RAM address 0x402f0400,
}

SECTIONS
{
	.text :
	{
		*(.text*);
	}> RAM

	.data :
	{
		*(.data*);
	}> RAM

	.bss :
	{
		*(.bss*);
	}> RAM
}

I'm new to the bare-metal programming and Cortex-A8,

Please guide me if something is missing from my side.

Thanks.