Hi, I have a test application on A55 which starts in EL3 mode, then switches to NSEL1 to execute some neon instructions. I noticed that the value of HCR_EL2.ID (bit 33) and HCR_EL2.CD (bit 32) will affect the behavior of neon instruction execution, which are:
The NEON instruction is：“str q0 [ x1，#0x60]”
Exception message: SPSR 0x3c9, ELR 0x400, ESR 0x82000010
If replace the NEON instruction to normal instruction “str x0 [x1, #60]”, it works well.
2. if both bits are 0, neon instructions works well in both NSEL1 and EL3.
On the technical manual, the ID bit and CD bit only affects the behavior of instruction cache and data cache in NSEL0 and NSEL1, and they should not related to neon operations.
Is there any clue that why HCR_EL2 value affects the neon instructions?
It more looks like an MMU problem.
Thanks. But we checked the register and found the MMU was not enabled in both EL3 and EL1...
Does x1 contain the same value when you test the NEON instruction in EL3?
Means: Is x1 aligned to 16bytes?
yes, x1 is aligned to 64 bytes.