In document on AXI3:
"The exclusive access monitor records the address and ARID value of any exclusive read
operation. Then it monitors that location until either a write occurs to that location or
until another exclusive read with the same ARID value resets the monitor to a different
address."
I have an example.
I have 2 Master and 2 bit ID per master. (out of order data & out standing address support)
M0 have master number is 0.
M1 have master number is 1.
When M0 is selected by the Arbiter, then M0 issue exclusive read to S0 with start address is 16h0000.
And then M1 is selected by the Arbiter, then M1 issue exclusive read to S0 with start address is 16h0000.
In two cases above, 2 exclusive read with same address is 16h0000 but different ARID.
What will happen with the monitor in my example???
After that, I assume that M1 issue exclusive write before M0.
What will S0 response to M0 and M1???
Best regards,
** Cao Phi
Thank you very much.
yasuhikokoumoto wrote: Hello Cai Phi, EXOKAY for M0 and OKAY for M1. Regarding the reads, these responses would be useless. It would be significant for writes (i.e. STREX), because whether success or fail of STREX depends on the response. Best regards, Yasuhiko Koumoto.
yasuhikokoumoto wrote:
Hello Cai Phi,
EXOKAY for M0 and OKAY for M1.
Regarding the reads, these responses would be useless.
It would be significant for writes (i.e. STREX), because whether success or fail of STREX depends on the response.
Yasuhiko Koumoto.