hi ,
I want to know the cycle information ,latencies of each instruction(secially vector instructions in A32 and A64) in coretex A53 architecture. It seems there is no document available which specifies the cycle timings. Can any one please provide the information.Fast response will be appreciated.
Thanks,
Sujatha.
Hi Sujatha,
I hope you are trying to compute theoretical values for your piece of code. But most of the cases it won't help you.
If I am not wrong there are few other features like dual issue, branch predictor which plays vital role. If you want to profile your code then use performance counters. If you want to estimate for the product then you may need refer to drystone or coremark values and also your SoC implementation.
Hope this helps.