I've been digging through the Technical Reference Manual (TRM) for the Cortex-A9 and so far it seems that it's possible to gather data about events such as hit and miss rates, but there doesn't seem to be anything on reading the raw data and tag bits. I've seen that under the DS-5 that there is a tool to view the cache, but that it is "dependent on the exact device and connection method." I've also seen under the ARM11 TRM a number of cache debug options and registers. I've come to the conclusion that either the Cortex-A9 doesn't support reading raw cache data, or there exists some documentation I haven't found or some tool is required in order to access that.
In particular I'm working with Xilinx's Zynq-based ZC702 and it would be wonderful if I could take snapshots of the cache contents. I realize that there would be performance hits, but I would only need to do this every so often. Either from within the processor or with an external tool would work as well.
Do tools like the DSTREAM and/or DS-5 allow you to view and debug the L1/L2 caches and give you access to data/statistics that aren't available otherwise?
Hi,
The Cortex-A9 doesn't include any mechanism for directly reading the contents of the Level 1 cache, and assuming the Level 2 cache is the L2C-310 then this doesn't include a method to directly read the cache contents either.
Sorry this isn't much help, and I'm afraid I don't have any specific knowledge on the particular device you mention nor DSTREAM/DS-5, but hopefully someone else can weigh-in with some information on these.
Dave
Hi all,
We'll confirm here that the ZC702 implements a Cortex-A9 with L2C-310 and therefore it isn't possible for the reasons above to have cache content reading on DSTREAM or via DS-5 (or any debugger for that matter).
Ta,
Matt
Hi Matt,
Your statement that L1 and L2 cache can not be directly queried on the ZC702 was very helpful (I had been banging my head against that wall, trying to figure out how to essentially verify cache coherency and read invalid cache values). Do you know where I could confirm that in the L2C-310 Technical Reference Manual?
Thanks for your help,
- Daniel.
Hi compumech,
You can't find it in the L2C-310 TRM because it isn't documented, because the feature doesn't exist to be documented. Neither the Cortex-A9 nor the L2C-310 have any method to read the contents of cache data or tag RAMs from a software or debugger perspective, at least nothing that ARM has provided for in those implementations. Vendors may implement their own methods to perform RAM testing which may be accessible somehow, but we wouldn't know where you'd look to find that information.