Cortex 8.2A : FEAT_SHA3

Also from CA55 manual:
B2.58  ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0, EL1
The ID_AA64ISAR0_EL1 provides information about the instructions implemented in AArch64 state,
including the instructions that are provided by the Cryptographic Extension.
Bit field descriptions
ID_AA64ISAR0_EL1 is a 64-bit register, and is part of the Identification registers functional group.
This register is Read Only.
The optional Cryptographic Extension is not included in the base product of the core. Arm requires
licensees to have contractual rights to obtain the Cryptographic Extension.

To me it means, you need to look at the SoC, to know if or if not the FEAT_SHA3 is implemented or not.

Also from CA55 manual:
B2.58  ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0, EL1
The ID_AA64ISAR0_EL1 provides information about the instructions implemented in AArch64 state,
including the instructions that are provided by the Cryptographic Extension.
Bit field descriptions
ID_AA64ISAR0_EL1 is a 64-bit register, and is part of the Identification registers functional group.
This register is Read Only.
The optional Cryptographic Extension is not included in the base product of the core. Arm requires
licensees to have contractual rights to obtain the Cryptographic Extension.

To me it means, you need to look at the SoC, to know if or if not the FEAT_SHA3 is implemented or not.

So, for the clarity of the thread and as a conclusion for question 1

 I can confirm Cortex A55 (ARM 8-2) do not implement SHA3.  it does implement AES and SHA-2 only.

I fell only ARM 8.4 will implement as it is becoming mandatory. I suspect only Apple do and no other implementation have been done.

We may find this feature on ARM 8.3 processor but i can't find any.

Regards