We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.
According to the Cortex-M3 trm r2p0(Issue H), Cortex-M3 has 3 reset input signals, PORESETn, SYSRESETn, and DAPRESETn.
Now I am thinking about a SOC with SW-DP and thinking of reducing the number of its terminals.
So I am thing that only SYSRESETn pin is equipped with the SOC and the others are always deasserted with pull-upped internally.
Can I have a debugger work correctly with such a SOC? Or PORESETn and DAPRESETn need to be controlled for a debugger?