We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.
Hello:
Suppose all exception Ievels support both big and little endian operation. According to the ARMv8 ARMARM, when exception taken from AArch32 state, the SPSR_EL1.E bit can control the endianess on executing an exception return operation in EL1, which means it can control the endianess of the EL0, if I am not missing something.
But there is also a contrl register named SCTLR_EL1, and the E0E bit do control the endianness of data accesses at EL0.
I am confused with the SPSR_EL1.E bit and the SCTLR_EL1.E0E bit. If they set the confilct configuration, what will the processer behave? Same with the SCTLR_EL2 and SPSR_EL2...
Regards, George.
Maybe this helps (DDI0487Fc_armv8_arm.pdf D4.3 ):If mixed endian support is implemented for an Exception level using AArch32, endianness is controlled by PSTATE.E. For exception returns to AArch32 state, PSTATE.E is copied from SPSR_ELx.E. If the target Exception level supports only little-endian accesses, SPSR_ELx.E is RES0. If the target Exception level supports only big-endian accesses, SPSR_ELx.E is RES1. PSTATE.E is ignored in AArch64 state.
OK, thanks a lot. It's clear in the Reference Manual.