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Which PMU Events for L2 Cache Misses on Cortex-A72

John Duffy

Hi

I want to monitor L2 cache misses through Linux perf, i.e. data that is not in the L2 cache and requires a main memory access, but I'm a bit confused which PMU events to use.

The Cortex-A72 TRM lists the following which seem likely candidates:

  • L2D_CACHE_REFILL
  • L2D_CACHE_REFILL_LD
  • L2D_CACHE_REFILL_ST
  • L2D_CACHE_INVAL

Which is a L2 cache miss?

What I'm trying to do is measure the effect of the L2 cache size on the performance of a CPU with 0.5MB L2 cache vs that of CPU with 1.0MB L2 cache.

Kind regards

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  • 0

    IMHO:
    REFILL: Loading cacheline because of any event, for example clearing it
    REFILL_LD: Loading it, because of a "load instruction"
    REFILL_ST: same, but store
    INVAL: Is invalidation of a cache line.

    So, I'd say, the sum of the REFILL* events gives the number of cache misses.

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  • 0

    IMHO:
    REFILL: Loading cacheline because of any event, for example clearing it
    REFILL_LD: Loading it, because of a "load instruction"
    REFILL_ST: same, but store
    INVAL: Is invalidation of a cache line.

    So, I'd say, the sum of the REFILL* events gives the number of cache misses.

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