There is a reference to erratum 820719 in the NXP S32V Errata list but I can't seem to find any reference to this erratum anywhere in ARM documentation. Is this erratum still valid?
Excerpt from S32V Errata document (refer: https://www.nxp.com/docs/en/errata/S32V234_1N81U.pdf )
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If one or more Cortex-A53 cores execute a stream of store instructions to non-reordereable Device memory, they might prevent a DSB instruction on another core in the processor from making progress.