unaligned transfers

Hi Norbert,

I do agree with virtually everything you write, an L1 cache can simplify things to some extent, and will usually improve master performance.

But where I still disagree is that unaligned access support complicates designs. As I mentioned previously slave (unless they are read sensitive) can ignore any AxADDR/AxSIZE misalignment. For write transactions the slave will see WSTRB indicate which byte lanes contain valid data (and this always needs checking because transfers can be sparse as well as unaligned), and for read transactions the slave can just return ARSIZE aligned data and let the master use the byte lanes it requested.

So the best option of all is for the SW to think of alignment when accessing data, but where the SW is not so tightly controlled you can use an L1 to improve performance and avoid unaligned accesses, and/or you support unaligned accesses when they are required, knowing that these don't complicate slave designs (unless your slave is also not supporting WSTRB), especially for non-cacheable transactions which should bypass the L1.

I'm not saying you are wrong, it's just that an L1 cache is not the only solution. As your Cortex-A master probably has an L1 it will reduce the occurence of unaligned transactions being needed to the memory system, but they are not a complication for slaves to support when they are needed. 

Hi Norbert,

I do agree with virtually everything you write, an L1 cache can simplify things to some extent, and will usually improve master performance.

But where I still disagree is that unaligned access support complicates designs. As I mentioned previously slave (unless they are read sensitive) can ignore any AxADDR/AxSIZE misalignment. For write transactions the slave will see WSTRB indicate which byte lanes contain valid data (and this always needs checking because transfers can be sparse as well as unaligned), and for read transactions the slave can just return ARSIZE aligned data and let the master use the byte lanes it requested.

So the best option of all is for the SW to think of alignment when accessing data, but where the SW is not so tightly controlled you can use an L1 to improve performance and avoid unaligned accesses, and/or you support unaligned accesses when they are required, knowing that these don't complicate slave designs (unless your slave is also not supporting WSTRB), especially for non-cacheable transactions which should bypass the L1.

I'm not saying you are wrong, it's just that an L1 cache is not the only solution. As your Cortex-A master probably has an L1 it will reduce the occurence of unaligned transactions being needed to the memory system, but they are not a complication for slaves to support when they are needed.