Hi experts and ARM designers,
I have found "ARM® Cortex®-M7 Processor Technical Reference Manual Revision r0p2" on the ARM site. By reading it I have a question. "Figure 1-3 Cortex-M7 functional diagram" shows all TCM accesses go through TCU. Does this mean CPU cannot access both ITCM and DTCM simultaneously? If it is correct, to locate DATA in DTCM is not useful in the performance view point because such accesses cannot be the Harvard Architecture. Is my understanding correct?
Best regards,Yasuhiko Koumoto.
Hi Peter,
what I would like to know is the Cortex-M7 TCU feature. Also my question is simple. Can one access from PFU to ITCM and the other access from LSU to D0/1TCM occur concurrently? There is no explanation of TCU in the Cortex-M7 Technical Reference Manual other than its block diagram. The following picture is the Cortex-R5 TCM interface (from the Technical Reference Manual). From PFU and LSU to ATCM and BTCM, the bus matrix seems to be a multi-layer. I think it can be possible to make the concurrent accesses of both PFU to ATCM and LSU to BTCM. Is it the same as Cortex-M7? Can you have the answer?