Hi,
I'm currently working on the IMX8QX which contains a cluster of 4 A35 cores. I'm trying to figure out to maximum interference possible between the 4 A35 cores. From the Cortex®-A35 technical reference manual, the Snoop control unit (SCU) seems to arbitrate the request coming from the cluster heading to the AXI interface. Is there any documentation which would provide more information about how the SCU does the arbitration? Is there a theoretical maximum value of the interference between cores? Also, if a core inside the cluster access a non cacheable region (device) would the SCU do the arbitration ?
Thanks for your support,
David
Hi David/Etienne,
The specifics of the NXP CA35 implementation would be best handled by the NXP support team. Have you created a case with them for those details? The Arm DS license entitles you to tool support on the CA35. Can you please send a query into support@arm.com so we can follow up there, please. Thanks! Mahesh
Isn't the arbitration among the 4 Cortex-A35 cores to the A35 cluster's L1 caches, L2 cache and Main Bus interface (AXI4/ACE/CHI memory bus) made by the SCU inside the cluster itself, which is an ARM product? Which parts of the arbitration policy/performance depends on the SoC vendor? (NXP)
i.MX 8X has 4 cores, a 128bits AXI4 memory bus, an L2 cache ECC. Not sure it has an ACP...
What do you mean by "Arm DS license entitles you to tool support on the CA35." How the compiler or IDE could help us understand the cores arbitration? Are you referring to example code? That's useful, but not what we are looking for.
Thanks,
Étienne