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Cortex A-35 cluster interference

Hi,

I'm currently working on the IMX8QX which contains a cluster of 4 A35 cores. I'm trying to figure out to maximum interference possible between the 4 A35 cores. From the Cortex®-A35 technical reference manual, the Snoop control unit (SCU) seems to arbitrate the request coming from the cluster heading to the AXI interface. Is there any documentation which would provide more information about how the SCU does the arbitration? Is there a theoretical maximum value of the interference between cores? Also, if a core inside the cluster access a non cacheable region (device) would the SCU do the arbitration ?

Thanks for your support,

David

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