Hi,
The AXI spec notes the dependencies between xREADY and xVALID for a Master as follows:
And even adds an important note:
However, I tried to figure out if this dependency is also true for 2 different consecutive Write transactions and I couldn't find any thing about it in the spec.
Consider the following example for implementing a Master that handles a single transaction at a time and doesn't advance to the next transaction till previous transaction is fully transmitted:
1st transaction is a burst with AWLEN>0. It starts with AWVALID and WVALID asserted and AWREADY and WREADY de-asserted. At a certain point AWREADY is asserted but WREADY remains de-asserted.
Can I stall AWVALID assertion for the 2nd transaction till WREADY is asserted for all beats of the 1st transaction? Doesn't it violate the guideline "master must not wait for the slave to assert AWREADY or WREADY before asserting AWVALID or WVALID"?
Same question is valid for a case where WREADY is asserted but AWREADY remains de-asserted, so WVALID for 2nd transaction is kept de-asserted till AWREADY assertion for 1st transaction.
Thank you Colin. Your answer is very helpful.