I am using an Atmel/Microchip ATSAME70 Cortex M7 processor and was working on getting Ethernet GMAC driver working. The GMAC uses an internal DMA engine to transfer packets to SRAM. I noticed that I was getting some HRESP errors with the DMA transferring data and the peripheral driver was not working. I disabled the data cache and the driver works.
The code polls the SRAM locations to see if a DMA has completed so I tried leaving data cache on and invalidating the cache before reading the SRAM but that did not fix problem. I was wondering if anyone knew of any problems using the data cache and DMAs in peripherals like this?
Note every time I contact Microchip about such problems they inform me that they never test/run code with caching enabled, so they never see any problems.
Thanks
Trampas
So I finally got the driver to work with the data cache enabled. I had to go through driver and find all the places the driver was transfering RAM buffers and make sure the data cache was flushed correctly before each one. I also noticed that some of the buffers were not explicitly aligned to correct byte boundaries, but as luck had it the compiler did align correctly. Here again the datasheet was unclear about byte boundaries and appeared to have contradictions, to be safe I aligned all the buffers.
Which datasheet? The core or the SoC one? Most often the SoC manual do not contain much info about the core.
The SoC (ATSAME70)...
Chapter 15.1 clearly tells the cache line size. ;-)
Yes... The ATSAME70 GMAC driver did not align the buffers for the GMAC DMA engine, even though the datasheet had mentioned a requirement that they were aligned.