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Question : The Definitive Guide to the ARM Cortex-M3

Kenichi Kenichi
Note: This was originally posted on 11th December 2007 at http://forums.arm.com

Dear, all.

I am new in this forum.
Recently I studying Cortex-M3 core, so I bought book "The Definitive Guide to the ARM Cortex-M3" by Joseph Yiu.
This book is very good book and this explains most of unaswered questions by TRM or AALRM.

As I found some mistake in this book, I would like to feedback, but I could not find publisher's homepage. Then I found Josephe's name in this forum, I would like to ask here.

In page 42, there is fig 3.11 and 3.12 but this contents is same as fig 3.8 and 3.9.
Fig 3.8 and 3.9 should be some program list.

Can I get correct figure? Or where I should contact?
Please advise.

Kenichi
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  • 0
    Note: This was originally posted on 23rd January 2010 at http://forums.arm.com

    Hi Miro,

    Good questions!

    In the case of having an IRQ running, and if the IRQ is lower priority than SysTick, then proceeding on context switching usually means the PSP is changed to point to the stack frame of a a different task.
    As a result, when you execute exception return, the PC value of another task will be used and you will end up executing the other tasks with privilege level of the IRQ, which can be bad (user task running at privileged level, and all other IRQs at the same or lower priority level will be blocked).  Therefore context switching code could modify LR to ensure it is switching to unprivileged level, but then it lead to usage fault due to trying to run in Thread mode with an active IRQ.

    In practice I believe Cortex-M3 will flag a usage fault even if LR is not modified because it has various system integrity checkings. When switching to the other task with IPSR equal 0 (which is unstacked from the other task's stack frame) and having an active IRQ should trigger a fault (need double check).

    Lower the SysTick priority is one solution, but if an IRQ handler is not function properly (e.g. accidental software deadloop) the SysTick will not be able to preempt and the system will be frozen.

    Yes, it if possible to have a mid-priority level SVC so that an OS aware IRQ handler can use the SVC function.  But instead of using SVC, you might able to call the SVC function directly rather than using SVC exception.  This is better if you need to port the software to Cortex-M0, which has 4 levels of priority levels.

    Hope this answered your questions and feel free to let me know if you need further explanations.
    regards,
    Joseph
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  • 0
    Note: This was originally posted on 23rd January 2010 at http://forums.arm.com

    Hi Miro,

    Good questions!

    In the case of having an IRQ running, and if the IRQ is lower priority than SysTick, then proceeding on context switching usually means the PSP is changed to point to the stack frame of a a different task.
    As a result, when you execute exception return, the PC value of another task will be used and you will end up executing the other tasks with privilege level of the IRQ, which can be bad (user task running at privileged level, and all other IRQs at the same or lower priority level will be blocked).  Therefore context switching code could modify LR to ensure it is switching to unprivileged level, but then it lead to usage fault due to trying to run in Thread mode with an active IRQ.

    In practice I believe Cortex-M3 will flag a usage fault even if LR is not modified because it has various system integrity checkings. When switching to the other task with IPSR equal 0 (which is unstacked from the other task's stack frame) and having an active IRQ should trigger a fault (need double check).

    Lower the SysTick priority is one solution, but if an IRQ handler is not function properly (e.g. accidental software deadloop) the SysTick will not be able to preempt and the system will be frozen.

    Yes, it if possible to have a mid-priority level SVC so that an OS aware IRQ handler can use the SVC function.  But instead of using SVC, you might able to call the SVC function directly rather than using SVC exception.  This is better if you need to port the software to Cortex-M0, which has 4 levels of priority levels.

    Hope this answered your questions and feel free to let me know if you need further explanations.
    regards,
    Joseph
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