I am trying to configure memory attribute for cortex R52 in our SOC which is having integrated L1 I/D Cache and no coherent agent.and having system RAM.
system is having two clusters with two cores each and other masters like DMA reside outside to the core subsystem having having access to the system RAM memory via the system bus.
So my question is Inner share attribute will share the memory b/w cores of same clusters and outer share attribute memory will share the share the memory with all the cores and with other masters like DMA ?
Not every bus master is connected to the caches. Most often only the CPU cores are. Esp. DMA is mostly left out of this. So if you do a DMA operations, you need to flush/invalidate the addresses where you DMA from/to.
Iam interested in this question. It makes sense to do cache maintenance, but what is the effect of switching from inner to outer? or would that have no effect in this configurations?
Thanks