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Cortex A8 Instruction Cycle Timing

barney vardanyan
Note: This was originally posted on 17th March 2011 at http://forums.arm.com

Hi) sorry for bad English

I need to count latency for two instruction, and all I have is the arm cortex A 8 documantation(charter 16) !
but I have no idea how can do this work using that documantation(
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    Note: This was originally posted on 5th May 2011 at http://forums.arm.com

    Thank you very much for sharing your experience. You have helped me a lot.
    I read from specs that a Neon load/store instructions can be dual issued with SIMD data-processing instructions. So I tried below code in your website:
    vld1.32 {d0}, [r0]
    vadd d1, d2, d3
    Mov r1, r2
    However, VADD is in separate cycle (cycle 4). Am I wrong?
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  • 0
    Note: This was originally posted on 5th May 2011 at http://forums.arm.com

    Thank you very much for sharing your experience. You have helped me a lot.
    I read from specs that a Neon load/store instructions can be dual issued with SIMD data-processing instructions. So I tried below code in your website:
    vld1.32 {d0}, [r0]
    vadd d1, d2, d3
    Mov r1, r2
    However, VADD is in separate cycle (cycle 4). Am I wrong?
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