• State Not Answered
  • Locked Locked
  • Replies 90 replies
  • Subscribers 346 subscribers
  • Views 80797 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Cortex A8 Instruction Cycle Timing

barney vardanyan
Note: This was originally posted on 17th March 2011 at http://forums.arm.com

Hi) sorry for bad English

I need to count latency for two instruction, and all I have is the arm cortex A 8 documantation(charter 16) !
but I have no idea how can do this work using that documantation(
Parents
  • 0
    Note: This was originally posted on 27th June 2011 at http://forums.arm.com

    I have 2 questions related to multiple load instructions. For example: ldm r1!, {r2, r3}.
    This instruction takes 2 cycle. So it is broken down to 2 single-cycle operations.
    1. Because write back is enabled, r1 is written in E2 stage. However, which single-cycle operation is r1 written? The first single-cycle operation or the second single-cycle operation?
    2. When are r2, r3 available for other instructions? I can not find any scheduling information in specs.
    I assume this instruction is similar to LDR, that means, r2, r3 is available in E3. Because r3 is written by the second single-cycle operation, it is available in E3 of the second single-cycle operation.

    If my assumption is correct, 2 below instructions should produce 2 cycle penalty:
    ldm r1, {r2, r3}
    ldr r4, [r3, #1]
    However, the result is different in http://pulsar.websha...sult.php?lng=fr
    Please explain for me.
Reply
  • 0
    Note: This was originally posted on 27th June 2011 at http://forums.arm.com

    I have 2 questions related to multiple load instructions. For example: ldm r1!, {r2, r3}.
    This instruction takes 2 cycle. So it is broken down to 2 single-cycle operations.
    1. Because write back is enabled, r1 is written in E2 stage. However, which single-cycle operation is r1 written? The first single-cycle operation or the second single-cycle operation?
    2. When are r2, r3 available for other instructions? I can not find any scheduling information in specs.
    I assume this instruction is similar to LDR, that means, r2, r3 is available in E3. Because r3 is written by the second single-cycle operation, it is available in E3 of the second single-cycle operation.

    If my assumption is correct, 2 below instructions should produce 2 cycle penalty:
    ldm r1, {r2, r3}
    ldr r4, [r3, #1]
    However, the result is different in http://pulsar.websha...sult.php?lng=fr
    Please explain for me.
Children
No data