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Cortex A8 Instruction Cycle Timing

barney vardanyan
Note: This was originally posted on 17th March 2011 at http://forums.arm.com

Hi) sorry for bad English

I need to count latency for two instruction, and all I have is the arm cortex A 8 documantation(charter 16) !
but I have no idea how can do this work using that documantation(
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  • 0
    Note: This was originally posted on 29th June 2011 at http://forums.arm.com


    n + 4

    Thank you very much for your information.
    I tested 2 below instructions:
    smlal r0, r1, r3, r4
    smlal r0, r1, r3, r4
    smlal takes 3 cycle, destination register is available in E5. So the first instruction releases r0, r1 at the cycle 3 + 5 = 8.
    Because the second instruction requires r1 in E1, it must start after the cycle 8.
    However, the counter module say it starts at the cycle 6 (http://pulsar.webshaker.net/ccc/sample-4830f428)
    Please explain this case for me.
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  • 0
    Note: This was originally posted on 29th June 2011 at http://forums.arm.com


    n + 4

    Thank you very much for your information.
    I tested 2 below instructions:
    smlal r0, r1, r3, r4
    smlal r0, r1, r3, r4
    smlal takes 3 cycle, destination register is available in E5. So the first instruction releases r0, r1 at the cycle 3 + 5 = 8.
    Because the second instruction requires r1 in E1, it must start after the cycle 8.
    However, the counter module say it starts at the cycle 6 (http://pulsar.webshaker.net/ccc/sample-4830f428)
    Please explain this case for me.
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