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When an exception is taken into account

Karolis

Hi

Related to ARMv7-M architecture:

I am searching through all infocenter documents but still cannot find anything and answer this question: "When an exception is taken into account?" I mean, are exceptions only serviced after the current instruction in instruction flow, or exception can interrupt current instruction in execution? I have found that exception servicing is asynchronous, but what does that mean? I understand that exception can arrive at any time, but when it is started to be serviced, when exception entry starts with respect to program flow?

Also, memory access instructions can be abandoned and restated. So, does that mean that it is possible to interrupt these instructions? Does it have something in common with memory attributes (normal, device, strongly-ordered)? Are other than memory access instructions also possible to interrupt/get them restarted? Where it is written in reference manual? What indicates that for CPU to do? Reference manual seems to be incomplete from this question point of view or I cannot find what I need. Hope you guys can help me. Thank you in advance.

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    Hi, you have to read ARMv7-M Architecture Reference Manual to find answers on your questions.

    "exception can interrupt current interrupt in execution?" - nested interrupts, when a higher priority interrupt can interrupt current interrupt handler in execution. All exceptions except Reset (-3), NMI (-2), HardFault (-1) have configurable priorities. During exception entry other exceptions can occur, either because of a fault on an operation involved in exception entry, or because of the arrival of an asynchronous exception, an interrupt, that is of higher priority than the current exception entry sequence.

    "exception servicing is asynchronous, but what does that mean? " - synchronous exception is generated by instruction execution synchronously to instruction stream (for example SVC); asynchronous exceptions are generated asynchronously to the program flow by peripherals (interrupts) or by imprecise faults due to the memory access instructions.

    "Also, memory access instructions can be abandoned and restated" - you can configure in System Control Block register the option of disabling or enabling interruption of load multiple and store multiple instructions. If you disable interruption of these instructions this increases the interrupt latency of the processor because any LDM or STM must complete before the processor can stack the current state and enter the interrupt handler. In another case load multiple and store multiple instructions can be interrupted and Execution Program Status Register will contain information about status of interruptible-continuable instructions.

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    Hi, you have to read ARMv7-M Architecture Reference Manual to find answers on your questions.

    "exception can interrupt current interrupt in execution?" - nested interrupts, when a higher priority interrupt can interrupt current interrupt handler in execution. All exceptions except Reset (-3), NMI (-2), HardFault (-1) have configurable priorities. During exception entry other exceptions can occur, either because of a fault on an operation involved in exception entry, or because of the arrival of an asynchronous exception, an interrupt, that is of higher priority than the current exception entry sequence.

    "exception servicing is asynchronous, but what does that mean? " - synchronous exception is generated by instruction execution synchronously to instruction stream (for example SVC); asynchronous exceptions are generated asynchronously to the program flow by peripherals (interrupts) or by imprecise faults due to the memory access instructions.

    "Also, memory access instructions can be abandoned and restated" - you can configure in System Control Block register the option of disabling or enabling interruption of load multiple and store multiple instructions. If you disable interruption of these instructions this increases the interrupt latency of the processor because any LDM or STM must complete before the processor can stack the current state and enter the interrupt handler. In another case load multiple and store multiple instructions can be interrupted and Execution Program Status Register will contain information about status of interruptible-continuable instructions.

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