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Is a DMB required between loading BASEPRI and storing BASEPRI_MAX?

Ramzyo

Hi,

I have a question regarding BASEPRI, BASEPRI_MAX, and DMBs as they relate to both the V7-M and V7E-M architectures.

Let's say I have the following assembly,

// stuff
mrs r0, BASEPRI
msr BASEPRI_MAX, #3
// more stuff

Is it necessary to put a DMB between the two instructions so that the processor doesn't reorder the memory accesses? After reading Chris Shore's article here and reading through the data sheet of the MCU that I'm working with, my understanding is that a DMB isn't necessary because the special registers are  'strongly-ordered' memory (or are they 'device memory'? Was a little confused about this). That being said, here's where my confusion comes in - BASEPRI and BASEPRI_MAX have different encodings in their system instructions (section B5.1.1 of the ARM v7-M Architecture Reference Manual [ARM DDI 0403E.b ID120114]). For a mrs instruction, BASEPRI_MAX is aliased to BASEPRI, however, this is not the case for a msr instruction. So, if the system instructions are different, does this imply that the processor treats the two instructions above as independent, and is therefore free to execute them in any order it pleases?

Thanks!

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  • 0 in reply to Ramzyo

    Hi Ramzyo,

    Thanks for your kind words.

    1. No.

    In Armv7-M architecture (https://developer.arm.com/docs/ddi0403/latest ) Section B5.2.3

    Visibility of changes in execution priority resulting from executing an MSR instruction
    If execution of a MSR instruction:
    •Increases the execution priority, the MSR execution serializes that change to the instruction stream.
    •Decreases the execution priority, the architecture guarantees only that the new priority is visible to instructions executed after either executing an ISB, or performing an exception entry or exception return.

    (it means if the MSR instruction set BASEPRI to 3, the interrupt of priority level 3 cannot take place, or if the processor already started accepting the interrupt, the MSR instruction must be abandoned and restart after the ISR completed).

    2.

    Yes, the order is maintained across exceptions.

    It is hard to follow the scenario you described, but as mentioned in (1), if the processor enter an ISR with priority level 3, BASEPRI should not be set to 3. It should work for both Cortex-M4, Cortex-M7, Cortex-M33 and Cortex-M35P.

    regards,

    Joseph

Reply
  • 0 in reply to Ramzyo

    Hi Ramzyo,

    Thanks for your kind words.

    1. No.

    In Armv7-M architecture (https://developer.arm.com/docs/ddi0403/latest ) Section B5.2.3

    Visibility of changes in execution priority resulting from executing an MSR instruction
    If execution of a MSR instruction:
    •Increases the execution priority, the MSR execution serializes that change to the instruction stream.
    •Decreases the execution priority, the architecture guarantees only that the new priority is visible to instructions executed after either executing an ISB, or performing an exception entry or exception return.

    (it means if the MSR instruction set BASEPRI to 3, the interrupt of priority level 3 cannot take place, or if the processor already started accepting the interrupt, the MSR instruction must be abandoned and restart after the ISR completed).

    2.

    Yes, the order is maintained across exceptions.

    It is hard to follow the scenario you described, but as mentioned in (1), if the processor enter an ISR with priority level 3, BASEPRI should not be set to 3. It should work for both Cortex-M4, Cortex-M7, Cortex-M33 and Cortex-M35P.

    regards,

    Joseph

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